There are several continuing areas of development and improvement for semiconductor device fabrication. One such area is device size. The size, including width, of a gate structure in metal-oxide-semiconductor field-effect transistor (MOSFET) devices continues to shrink, providing benefits such as increased density and reduced power. Another area is the use of MOSFET devices having a high dielectric constant (high-k) material and a metal gate.
Yet another avenue of inquiry is the development of three-dimensional designs, such as a fin-like field effect transistor (FinFET). A FinFET can be thought of as a typical planar device extruded out of a substrate and into the gate. A typical FinFET is fabricated on a thin “fin” (or fin structure) extending upwards from the body from the substrate, and may be formed by depositing fin material on the substrate, etching non-fin areas of the substrate, or a combination thereof. The channel of the FET is formed in this vertical fin, and a gate is provided over (e.g., wrapping) the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from both sides. This may result in higher current flow, a reduction in short channel effect, and other advantages. The present disclosure provides improvements that relate to the fabrication of planar devices as well as FinFETs and other non-planar devices.